Technical Field
The present disclosure relates to a circuit and to a method for generation of a clock signal, with the possibility of adjustment of the duty cycle.
Description of the Related Art
As it is known, clock signals are used for timing the operations of a large number of circuits, both analog and digital.
As illustrated in FIG. 1, a clock signal ck typically has a square-wave pattern with a given period T. The duty cycle d represents, in a known way, the active percentage of time of the period, designated by T in FIG. 1, with respect to the total period:
  d  =      τ    T  
In the digital field, the clock signals may, for instance, be used for synchronizing the operations of data communication. It is, for example, important to know the duration of the “high” and “low” levels of the clock signal in order to guarantee the so-called “setup” and “hold” times in combinatory logic, i.e., the minimum times required for a datum to remain stable before and after an edge, for example the rising edge, of the clock signal.
In the analog field, clock signals are used, for example, in switched-capacitor amplifier circuits, in which the presence of two phases is typically required, a “high” phase and a “low” phase, of appropriate duration, represented by the “high” level and “low” level of the clock signal. For instance, these phases may be used for timing operations of reset, or detection of an analog input signal. Given a certain period of the clock signal, the durations of the high and low phases must be selected appropriately, sometimes differing from one another to guarantee proper operation and settling of the circuit.
A large number of solutions have been proposed for generation of clock signals, having an adjustable duty cycle. The present Applicant has, however, found that none of these solutions is altogether satisfactory in terms, for example, of complexity and electric-power consumption.
For instance, a possible known solution is illustrated in FIG. 2 and is described in detail in the document: “High-speed Programmable Counter Design for PLL Based on A Delay Division Technique”, Hui Zhang, Hai-gang Yang, Jia Zhang, Fei Liu—2009 IEEE International Symposium on Radio-Frequency Integration Technology.
According to this solution, a clock-signal generator circuit 1 envisages the use of an input clock signal, so-called “master”, designated by ckin, which has a high frequency and is supplied at the input of an n-bit digital counter 2.
The counter signal count generated by the digital counter 2 is supplied at the input of a first digital comparator 3 and of a second digital comparator 4, which compare it with a first threshold value M and a second threshold value N, respectively.
The output of the first digital comparator 3 is used as set signal S for an output flip-flop 5, whereas the output of the second digital comparator 4 is used as reset signal R for the same output flip-flop 5. The set signal S is further used for resetting the counter count supplied by the digital counter 2.
The output Q of the output flip-flop 5 provides the output clock signal ckout, the duty cycle of which and the period of which may be regulated by selecting the appropriate threshold values M and N (which regulate, respectively, the high phase and the low phase of the clock signal). In particular, the duty cycle is in this case a function of the ratio N/M between the aforesaid threshold values.
The present Applicant has, however, realized that the clock-signal generator circuit 1, illustrated in FIG. 2, has some disadvantages, amongst which: a master clock signal ckin is required having a high frequency for accurate adjustment of the value of duty cycle; the resolution that may be obtained for the duty cycle depends upon the number of bits n of the digital counter 2; a high resolution requires a greater occupation of area in integrated implementation and a greater power consumption; it is possible to obtain only a certain number of discrete values for adjustment of the duty cycle.
A further known solution for a clock-signal generator circuit 1′ is illustrated in FIG. 3 and described in detail in the document: “A Duty-Cycle Control Circuit With High Input-Output Duty-Cycle Range”, R. Tajizadegan, A. Abrishamifar—15th International Conference, MIXDES 2008, Poland.
This further solution is based in general on a delay-locked loop (DLL), which envisages the use of a delay line 6, receiving an input clock signal, once again designated by ckin, and formed by a chain of a certain number p of delay logic gates 7, with variable and adjustable delay, connected together in series. The output of this chain of delay logic gates 7 is closed in a loop feedback path towards the input.
The phase difference between the input clock signal ckin and the output clock signal ckout (given by the cumulative delay of the various delay logic gates 7) is zero or known in steady-state conditions, owing to the presence of a phase-frequency detector (PFD) 8, which measures the phase offset of the voltages across the chain and controls, through a biasing generator 9, the delay of the individual delay logic gates 7, via application of an appropriate control signal.
The voltages on the output of each delay logic gate 7 represent respective divisions of the input clock signal ckin.
The present Applicant has realized that also this further solution has some disadvantages, amongst which the following: the resolution that may be obtained for the duty cycle depends on the length of the delay line 6, so that a greater resolution requires a greater number p of delay logic gates 7 (and a consequent increase in occupation of area and electric power consumption); the DLL is based on the precise coupling between the various delay logic gates 7, so that the use of a large number of such delay logic gates 7 (to obtain a high resolution) exposes to problems of linearity; also in this case, it is possible to obtain only a certain number of discrete values for the duty cycle.